Present complementary metal oxide semiconductor (CMOS) synchronous dynamic random access memory (SDRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. Advances in system technology require ever increasing clock rates and memory bus widths to achieve high data rates. Both of these methods, however, are subject to practical limitations. Increased clock rates increase system cost due to a need to reduce parasitic loading. Increased memory bus widths fulrther increase system cost by increasing memory package pin counts, thereby increasing memory package size and a required number of printed circuit board traces.
A proposed solution to these problems was presented by K. Nogami & A. El Gamal, A CMOS 160 Mb/s Phase Modulation I/O Interface Circuit, ISSCC Digest of Technical Papers, February 1994 at 108. Nogami et al. present a circuit for transmitting and receiving multiple data bits over each input/output (I/O) pin in a single clock cycle. Each clock cycle is divided into 2.sup.N phases or respective time slots. A logic state of each of N data bits corresponding to a single I/O pin, determines the respective time slot during which a data signal is transmitted or received. Thus, multiple data bits are phase modulated and simultaneously transmitted or received during a single clock cycle.
Nogami et al. use a voltage controlled oscillator (VCO) and phase locked loop (PLL) circuit to maintain stable phase positions with variations in temperature, supply voltage and the manufacturing process. The VCO and PLL circuits, however, increase circuit complexity and power consumption. Moreover, Nogamni et al. require a periodic reference cycle within data cycles compensate for VCO frequency drift. This periodic reference cycle interrupts data transmission and imposes an additional task on the system processor or memory controller. Finally, Nogami et al. require synchronization with a system clock. This imposes a significant limitation on large circuits such as memory systems, since propagation delay of the system clock may be substantially different from a propagation delay along an I/O bus.